The present invention relates generally to integrated circuit testing techniques and, more particularly, to a design structure for shutting off data capture across asynchronous clock domains during at-speed testing.
The testing of integrated circuits has evolved into a highly developed area of technology. Generally such testing may be implemented through the use of external equipment, Built-In Self-Test (BIST) circuitry, or a combination of the two. Typically, all test methodologies involve shifting data into scannable memory elements of an integrated circuit device (e.g., Level Sensitive Scan Design or LSSD latches), capturing the input to the memory elements, shifting the captured data out and then comparing the captured data with predetermined values to determine whether the circuit has performed according to design. Automatic test pattern generation (ATPG) systems use tools for testing digital circuits after the circuits have been manufactured. In general, an ATPG tool generates a set of test vectors that are applied to a circuit under test. The output of the circuit is analyzed to identify logic faults in the circuit design (i.e., “functional testing”), as well as detecting fabrication defects (i.e., “structural testing”).
“At-speed” testing refers to testing techniques to detect defects that are only apparent when the circuit is running at system speed. Many time-based defects cannot be detected unless the circuit is run at-speed. Examples of time related defects that occur at-speed include high impedance shorts, in-line resistance, and cross talk between signals. One problem of particular concern in regard to at-speed structural testing (ASST) relates to the effects of clock skew (i.e., misalignment of clock signals between clock domains) when signals are exchanged between different clock domains in the circuit at high test-clock speeds. The testing of multiple asynchronous clock domains simultaneously while using functional clocks generated by phase locked loops (PLLs) is difficult because it is impossible to predict the relative positions of clock edges generated by asynchronous PLLs. Existing solutions to the problem of testing multiple asynchronous clock domains include testing only one clock domain at a time, and/or inserting a wrapper of latches or flip-flops between clock domains, and/or ensuring that for each scan chain, all the latches belong to the same clock domain. Thus, only a few scan chains have test data for each test pattern shifted therein. The test still addresses only one domain at a time; however the total time required for scan is now reduced. Unfortunately, such approaches are disadvantageous in that they result in increased test data volume, increased testing time, and an increased hardware overhead.
Accordingly, it would be desirable to be able to simultaneously test the logic in asynchronous clock domains in an economical manner.